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5962-0625501QXC
Data Sheet October 29, 2007 FN6490.1
350MHz Fixed Gain Amplifiers with Enable
The 5962-0625501QXC is a fully DSCC SMD compliant part and the SMD data sheet is available on the DSCC website (http://www.dscc.dla.mil/programs/specfind/default.asp). The 5962-0625501QXC is electrically equivalent to the EL5106. Reference equivalent "EL" data sheet for additional information. The 5962-0625501QXC is a fixed gain amplifier with a bandwidth of 350MHz. This amplifier is ideal for today's high speed video and monitor applications. It features internal gain setting resistors and can be configured in a gain of +1, -1 or +2. With a supply current of just 1.5mA and the ability to run from a single supply voltage from 5V to 12V, these amplifiers are also ideal for handheld, portable or battery powered equipment. The 5962-0625501QXC has an enable and disable function to reduce the supply current to 25A typical. Allowing the CE pin to float or applying a low logic level will enable the amplifier.
Features
* Gain selectable (+1, -1, +2) * 350MHz -3dB BW (AV = 2) * 1.5mA supply current per amplifier * Fast enable/disable * Single and dual supply operation, from 5V to 12V
Applications
* Battery powered equipment * Handheld, portable devices * Video amplifiers * Cable drivers * RGB amplifiers
Pinout
5962-0625501QXC (10 LD FLAT PACK) TOP VIEW
1 2 3 4 5 NC ININ+ VSNC NC NC CE VS+ OUT 10 9 8 7 6
Ordering Information
PART NUMBER (Note) 5962-0625501QXC PART MARKING 06255 01QXC PACKAGE PKG. DWG. #
10 Ld Flat Pack K10.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
5962-0625501QXC
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) Flat Pack Package (Notes 1, 2) . . . . . . 165 60 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . .-55C to +125C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.8mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, RL = 150, TA = +25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
AV = +1 AV = -1 AV = +2
250 380 350 20
MHz MHz MHz MHz V/s ns nV/Hz pA/Hz %
BW1 SR tS eN iN+ dG dP
0.1dB Bandwidth Slew Rate 0.1% Settling Time Input Voltage Noise IN+ Input Current Noise Differential Gain Error (Note 3) Differential Phase Error (Note 3) AV = +2 AV = +2 VO = -2.5V to +2.5V, AV = +2 VOUT = -2.5V to +2.5V, AV = 2
4500 16 2.8 6 0.02 0.04
DC PERFORMANCE RF, RG Internal RF and RG 325
INPUT CHARACTERISTICS RIN CIN ENABLE tEN tDIS NOTE: 3. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz Enable Time Disable Time 280 400 ns ns Input Resistance Input Capacitance at IN+ 2 1 M pF
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FN6490.1 October 29, 2007
5962-0625501QXC Pin Descriptions
5962-0625501QXCIS (10 LD FLAT PACK) 1, 5, 9, 10 2 PIN NAME NC INFUNCTION Not connected Inverting input EQUIVALENT CIRCUIT
IN+
RG RF
IN-
CIRCUIT 1
3 4 6
IN+ VSOUT
Non-inverting input Negative supply Output
(Reference Circuit 1)
OUT RF
CIRCUIT 2
7 8
VS+ CE
Positive supply Chip enable
VS+
CE
VSCIRCUIT 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 3
FN6490.1 October 29, 2007
5962-0625501QXC Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
e
-Ab PIN NO. 1 ID AREA E1 0.004 M H A-B S DS 0.036 M -B-
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A A D
INCHES SYMBOL A b b1 MIN 0.045 0.015 0.015 0.004 0.004 0.240 0.125 0.030 0.008 0.250 0.026 0.005 10 MAX 0.115 0.022 0.019 0.009 0.006 0.290 0.260 0.280 0.015 0.370 0.045 0.0015
MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.10 3.18 0.76 1.27 BSC 0.20 6.35 0.66 0.13 10 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 7.37 6.60 7.11 NOTES 3 3 7 2 8 6 Rev. 0 3/07
S1 H A-B S DS
c c1 D E E1 E2 E3 e k L Q S1 M N
Q A -C-
E
C -D-H-
L E3
E2 E3 LEAD FINISH
L
SEATING AND BASE PLANE
0.050 BSC
c1
BASE METAL b1 M M (b) SECTION A-A
(c)
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
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FN6490.1 October 29, 2007

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